IT News on September 30th: Technology media NotebookCheck published a blog post today (September 30th) reporting that Nuvacore has made public the development model for its WarpCore processor cores. Before deciding on the instruction set (such as x86, Arm, or RISC-V), they build most of the underlying microarchitecture first.

IT reported in April of this year that Nuvacore was co-founded by Gerard Williams III, John Bruno, and Ram Srinivasan. All three individuals possess extensive experience in custom CPU design.

Williams initially worked at Arm for 12 years, where he designed several key architectures including Cortex-A8 and Cortex-A15. After transitioning to Apple from Arm, he took on the role of chief architect for Apple's self-developed mobile chips, such as A12X-A17. He is also the inventor of over 60 Apple patents, which mainly cover technologies in power management and multi-core scheduling.

After leaving Apple, Gerard Williams III founded his own company, NUVIA. Subsequently, in 2021, Qualcomm acquired this company for $1.4 billion, which is approximately 9.565 billion yuan at current exchange rates. Gerard Williams III also joined Qualcomm at that time, taking on the role of Senior Vice President of Engineering.

The architecture Oryon CPU (originally Nuvia Phoenix) that he led the development of later became an important technical foundation for the Snapdragon 8 Elite Gen 5 (the fifth-generation Snapdragon 8 Premium Edition) and the Snapdragon X Elite.

In addition to Williams, Nuvacore has also hired former Apple CPU engineering director David Williamson to serve as the Senior Vice President of Hardware Engineering.

According to the details officially released, Nuvacore refers to its development model as "core priority" ( Core First ). Traditional CPU projects usually start from the target instruction set architecture ( ISA ), whereas Nuvacore plans to first establish a foundational CPU core, and then determine the ISA based on product or partner requirements. In the latest tweet, it was stated: "We said we wanted to rewrite the rules of the silicon (semiconductor/chip) industry, and we mean it."

The company stated that after decoupling some microarchitectures from ISA, the engineering team can focus on improving performance, energy efficiency, and chip area first. However, the delayed determination of ISA does not mean that any instruction set can be directly integrated later on. Instruction decoding, privilege levels, memory ordering, exception handling, and software compatibility will still limit the design of CPU.

In addition, the authorization requirements for different ISA also vary: RISC-V generally does not require an architecture license in the Arm format; implementation of Arm requires corresponding architectural authorization; while the implementation rights for x86 are strictly controlled.